1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device configured by using electrically rewritable nonvolatile memory cells.
2. Description of the Related Art
A NAND type flash memory is known as a nonvolatile semiconductor memory device that is electrically rewritable and suitable for high integration. In a NAND type flash memory, a NAND cell unit is configured by series-connecting a plurality of memory cells in a manner that a source diffusion layer of one memory cell is shared as a drain diffusion layer of its adjoining memory cell. Both ends of the NAND cell unit are connected to a bit line and a source line via select gate transistors respectively. Such a NAND cell unit configuration enables a smaller unit cell area and a larger memory capacity than those of a NOR type memory.
A sense amplifier of a semiconductor memory device such as a NAND type flash memory determines data basically by detecting the presence or absence or the level of a cell current that flows in accordance with the data in a memory cell. The sense amplifier is normally connected to a data line (bit line) connected to a plurality of memory cells. The sensing scheme of the sense amplifier is roughly divided into a voltage sensing type and a current sensing type.
For example, a voltage sensing type sense amplifier pre-charges a bit line disconnected from the memory cells to a certain voltage, causes a selected memory cell to discharge the bit line, and senses the discharge state of the bit line at a sense node connected to the bit line. In the data sense, the bit, line is disconnected from a current source load, and the bit line voltage determined by the cell data is sensed. On the other hand, a current sensing type sense amplifier executes data sense by causing a reading current to flow into a memory cell through a bit line. Determination of data is finally done by detecting a difference in voltage at a sense node that is connected to a bit line. The difference in voltage at the sense node is caused by a difference in cell current.
The voltage sensing type sense amplifier and the current sensing type sense amplifier generally have the following merits and demerits. The voltage sensing type senses a discharge state of the bit line after it is precharged, and hence consumes less electricity. However, a large-capacity memory with a large bit line capacitance takes a long time to charge and discharge the bit line, and hence it is difficult to perform a fast sense operation. Further, the voltage sensing type causes a relatively large amplitude of the bit line voltage depending on cell data, and thus noise between adjoining bit lines becomes a problem.
On the other hand, the current sensing type sense amplifier can realize a fast sense operation by executing data sense by causing a reading current to flow into a memory cell through the bit line. A clamp transistor disposed between the bit line and a sense amplifier controls the bit line potential to a constant voltage all the time during the sense operation, thereby eliminating influence between adjoining bit lines. Accordingly, an ABL (All Bit Line) type sense amplifier is used for the current sensing scheme which realizes parallel sensing of all the bit lines. Further, in order to prevent the current sensing type sense amplifier from being influenced by adjoining channels in the sense operation, a method is proposed in which a reading operation is performed for every other bit line at a time, while grounding the remaining bit lines that are not data reading target, thereby using the grounded bit lines as shield lines.
The current sensing type sense amplifier consumes more electricity than the voltage sensing type sense amplifier does because it executes sensing by causing a current to flow. Recently, as device miniaturization advances, the capacitance of the bit lines increases, leading to a problem that a large current is consumed when charging the bit lines. The voltage sensing type can limit the current when charging the bit lines by means of a current control circuit. However, if the current sensing type uses a power supply limited by a current control circuit in an operation of causing a current to flow through all the bit lines, the current flowing through the bit lines is not determined by the threshold of the memory cells, but is determined by the load of the current control circuit, which might result in erroneous data sense. Therefore, the current sensing type sense amplifier has to connect the power supply directly thereto without a current control circuit, thus allowing a large current to flow when charging the bit lines. Here, a nonvolatile semiconductor memory device is known which has a configuration for dispersing peak currents in a read operation by delaying the pre-charging operation of the bit lines by a certain time period among respective memory banks based on a control signal delayed by a delay circuit.
A data write operation of a NAND type flash memory is executed on a page basis by defining memory cells arranged along a selected word line as one page. Specifically, a write operation is executed as an operation of supplying a writing voltage to a selected word line and injecting electrons into a floating gate electrode from a cell channel under the effect of FN tunneling. In this case, the potential of the cell channel is controlled in accordance with whether the data to be written is “0” or “1”.
That is, when writing data “0”, a voltage VSS is supplied to a bit line and transferred to the channel of the selected memory cell via the select gate transistor which is electrically conductive. At this time, in the selected memory cell, a high electrical field is applied across the floating gate electrode and the channel, and hence electrons are injected into the floating gate electrode. In response to this, the threshold voltage distribution shifts toward the positive direction. On the other hand, when writing data “1” (non-write), a voltage VDD is supplied to a bit line to charge the cell channel up to a voltage VDD-Vth (Vth is the threshold voltage of the select gate transistor), and then the cell channel is brought into a floating state. At this time, the potential of the cell channel rises due to capacitance coupling with the word line, thus prohibiting electron injection into the floating gate electrode. Hence, the threshold voltage distribution does not shift.
As the capacity of the NAND type flash memory increases, the number of bit lines increases. Furthermore, the voltage VDD for charging the bit lines in a write operation is higher than the voltage for charging the bit lines in a read operation. Therefore, when charging the bit lines up to the voltage VDD in a write operation of the memory, there is a problem that the total of the currents flowing through all the bit lines becomes large.